TOPOLOGY
The basic principles behind the neutral point clamped transformerless inverter are very similar to those of a simple buck converter. The main difference is that instead of merely switching the output between the high and low rails, the npc inverter also switches to a middle point (the neutral point), which is created by two large capacitors. As a result, the switching node is connected to three different levels rather than just two, as can be seen in the diagram below.
This multi level switching allows for smoother output waveforms, greater efficiency (albeit at greater cost), and lower power requirements for the inner two FETs. As can be seen in the diagram below, the switching node is connected to VDC+ when the top two FETs are turned on. VDC+ is higher than the voltage of the neutral point, so the diode attached to the node between the two FETs remains off. The switching node is connected to GND when the bottom two FETs are turned on. GND is lower than the voltage of the neutral point, so the diode attached to the node between the two FETs remains off. The switching node is connected to the neutral point when the middle two FETs are on. When current is exiting through the node, the higher diode turns on, clamping the node to the neutral point. When current is entering through the switching node, the lower diode turns on, also clamping the node to the neutral point.
NPC inverters typically, but not necessarily, have two additional phases (three in total, each 120˚ apart) so that they can interface directly to the power grid. This allows for the clever trick of connecting the output filtering capacitors between the different phases rather than to GND so that the superposition of the off-phase waveforms results in an even smoother five step waveform to filter, as can be seen below.
Once the group had fully grasped the basics of the NPC topology outlined above and chosen a set of parts, we expected the implementation of the remaining circuitry to be relatively trivial, using off the shelf gate drivers to interface between the MCU and the FETs. To our dismay, however, we were unable to find any gate drivers whatsoever that were designed to operate the higher two FETs and had to implement custom circuitry to deliver power to general purpose high side gate drivers that would then drive the higher two FETs. The details of this circuit turned out to be very nontrivial and are thus outlined separately in the next section.